The L3 cache is the last level of on-chip Cache before a miss has to go all the way to main memory. It is the largest level (tens of megabytes is common on server chips) and the slowest of the three, but still an order of magnitude faster than DRAM. Because DRAM latency is so punishing, L3's job is less about serving the hottest data (L1 already does that) and more about keeping the miss rate to DRAM as low as possible.
L3 is typically shared across all cores on a chip (or all cores in a chiplet, on multi-chiplet designs), unlike the private L1 and usually-private L2. Sharing means one core can benefit from data another core already pulled in, which is common in workloads where multiple threads touch the same data structure. It also means L3 doubles as a natural point for Cache coherence bookkeeping, since a directory-based protocol can attach sharer-tracking metadata directly to the L3 tags rather than maintaining a separate structure.
On many-core chips, L3 is physically divided into per-core slices connected by an on-chip ring or mesh interconnect, rather than built as one monolithic block. An address is hashed to a specific slice, so a request from any core may have to travel across the interconnect to reach the slice that owns that address. This adds variable latency depending on physical distance, which is part of why memory access on large multi-socket systems is non-uniform even before DRAM is involved.