The L1 cache is the first and fastest level of the Cache hierarchy, sitting directly next to a single core. It is small on purpose, typically 32 KB to 64 KB, because access latency grows with capacity: a bigger L1 would mean a slower L1, and the whole point of L1 is to serve the hottest data in as few cycles as possible (commonly 4-5 cycles on modern x86 cores).

Unlike L2 and L3, L1 is almost always split into two physically separate caches: the L1i (instruction cache) and L1d (data cache). Splitting them lets instruction fetch and data load/store happen in the same cycle without contending for the same read port, which matters because both operations are needed on every single instruction executed.

        +--------+
        |  L1i   |  <- instruction fetch
core -> +--------+
        |  L1d   |  <- load/store
        +--------+

L1 is private to its core; it is not shared with sibling cores the way L3 usually is. This keeps access latency low, since there's no cross-core arbitration, but it also means the same cache line can end up duplicated across several cores' L1s, which is exactly the scenario Cache coherence protocols exist to manage. A core writing to a line it holds in L1 has to coordinate with any other core's L1 that also holds a copy.