NUMA (Non-Uniform Memory Access) describes a multi-socket system where each processor has its own local bank of memory, but can also reach memory attached to other sockets over an Interconnect. Access latency to local memory is lower than access to remote memory, and the gap grows with the number of sockets and hops involved. This is the opposite of a UMA (Uniform Memory Access) design, where every core sees the same latency to any address regardless of which socket issued the request.

Socket 0                 Socket 1
[cores] -- local RAM      [cores] -- local RAM
    \                          /
     \------ interconnect ----/
      (remote access: slower)

A single memory controller can only serve so many memory channels before trace length and electrical fan-out become the bottleneck. Giving each socket its own local memory controller and RAM lets total memory bandwidth scale with socket count instead of being capped by one shared controller, at the cost of making some accesses slower than others. This tradeoff is unavoidable once a system grows past a single socket. it's the reason NUMA, not UMA, is the norm on multi-socket servers.

Placement matters: a thread pinned to socket 0 that repeatedly touches memory allocated on socket 1 pays the remote-access penalty on every access, even though the same code would run faster if either the thread or the memory moved to match. Most NUMA-aware allocators default to first-touch placement, allocating a page on the socket of whichever thread first writes to it, which works well when the thread that allocates a buffer is also the one that will use it most. Software that ignores this (allocating everything up front on one thread, then handing pieces out to worker threads on other sockets) can end up with most memory traffic crossing the interconnect regardless of how well the computation itself is parallelized. Tools like numactl and libnuma exist specifically to let a program control or query this placement explicitly rather than leaving it to chance.

NUMA compounds with ordinary Cache effects rather than replacing them: even before NUMA distance enters the picture, a cache miss inside a single socket already costs far more than a hit. NUMA adds a second, coarser-grained latency tier on top, so the effective memory hierarchy on a multi-socket machine is really L1 → L2 → L3 → local DRAM → remote DRAM, not just the three cache levels alone.