Cache coherence is the guarantee that all cores see a single, consistent view of memory even though each core may hold its own private copy of a line in L1 or L2. Without it, one core could write to its cached copy of a variable while another core keeps reading a stale copy from its own cache indefinitely, since neither core has any reason to know the other's cache exists.
Core A: L1 has x = 0 Core B: L1 has x = 0 Core A writes x = 1 (only Core A's L1 and maybe L2 know) Core B reads x (still sees 0, unless something intervenes)
A coherence protocol is the “something” that intervenes: it makes sure Core A's write either invalidates or updates Core B's copy before Core B's read is allowed to complete.
Coherence protocols fall into two broad families, differing in how a core discovers that another core holds a copy of a line it wants to write or read.
Snooping protocols (Cache snoopy protocols) rely on a shared bus that every cache listens to. Every core broadcasts its reads and writes on the bus, and every other core's cache watches (“snoops”) the traffic to see if any of it concerns a line it holds. This works well when the number of cores is small enough that a shared bus can carry the broadcast traffic without becoming the bottleneck.
Directory-based protocols (Cache directory protocols) replace broadcast with a lookup: a directory tracks which cores hold a copy of each line, so a write only has to message the specific cores listed as sharers instead of shouting to everyone. This scales to many more cores than snooping, at the cost of the directory itself becoming an extra structure to maintain and query.
Coherence is often confused with memory consistency, but they answer different questions. Coherence guarantees that writes to the same location become visible to all cores in some agreed order. Consistency (see memory-order) governs the visible ordering of writes to different locations relative to each other. A machine can be fully coherent and still allow two cores to observe writes to two different variables in different orders, which is exactly what weaker memory orders like memory_order_relaxed permit.