L3 cache is the last level of on-chip cache before DRAM, typically tens of megabytes on server chips. It is shared across all cores on a chip and much slower than L1/L2 but still orders of magnitude faster than DRAM. On many-core designs, L3 is divided into per-core slices connected by an on-chip mesh or ring interconnect.

L3 serves as both a shared resource for multi-threaded workloads and a natural point for cache-coherence bookkeeping in directory-based protocols.

This example shows L3 cache effects with large arrays exceeding L2 capacity.

// compile: gcc -O2 -o l3cache l3cache.c
// run: ./l3cache
// description: measure L3 cache latency with large array access
 
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <string.h>
 
#define SIZE_L3 8388608  // ~8MB, fits in L3
 
int main() {
    int *arr = malloc(SIZE_L3 * sizeof(int));
    memset(arr, 0, SIZE_L3 * sizeof(int));
 
    clock_t start, end;
    volatile int sum = 0;
 
    start = clock();
    for (int i = 0; i < SIZE_L3; i += 256) {
        sum += arr[i];
    }
    end = clock();
    printf("L3 access time: %ld cycles\n", end - start);
 
    free(arr);
    return 0;
}