MSI

MSI (Modified/Shared/Invalid) is the baseline write-back snoopy coherence protocol. Unlike WTI, a core can write to a line and keep the new value only in its own cache, deferring the write-back to memory until the line is evicted or another core needs it. This trades WTI's per-write memory traffic for a small amount of extra state to track per line.

• Modified (M) — this cache holds the only copy, and it is dirty (different from memory). No other cache holds the line.
• Shared (S) — this cache holds a clean, read-only copy, and zero or more other caches may hold the same clean copy.
• Invalid (I) — this cache does not hold a valid copy.

        read miss                    write miss / other's write
   I --------------> S <--------------------------------- M
   |                 |                                     ^
   | write miss      | write hit (must invalidate sharers)  | write hit
   v                 v                                      |
   M <---------------+--------------------------------------+

A read that misses pulls the line in as Shared. A write always needs exclusive ownership, so a write to a Shared line first broadcasts an invalidate to every other sharer, then transitions to Modified. A write to an already-Modified line (held only locally) needs no bus transaction at all, since no other cache can have a copy to invalidate. When another core's read or write is snooped for a line this cache holds as Modified, the dirty data must be supplied (write-back to memory, or a cache-to-cache transfer depending on the implementation) before the requester can proceed.

MSI has one inefficiency: writing to a line that no other cache holds still has to go through the Shared state and issue a bus invalidate, because a plain read miss can't tell whether it's the only copy in the system. MESI adds an Exclusive state precisely to distinguish that case, letting a write to an uncontended line skip the bus entirely.