MESI (Modified/Exclusive/Shared/Invalid) extends MSI with one extra state, Exclusive, to handle a very common case more cheaply: a core reads a line that no other cache currently holds, then shortly afterward writes to it. Under plain MSI that write still has to broadcast an invalidate on the bus, even though there was nothing to invalidate. MESI's Exclusive state remembers that the line was uncontended at load time, so the later write can proceed silently.
A read miss loads a line as Exclusive if the bus snoop shows no other cache responds as holding it, and as Shared if another cache does respond. From Exclusive, a local write is free: since no one else has a copy, the transition to Modified needs no bus transaction, just a local state change. From Shared, a write still needs the MSI-style invalidate broadcast, because other caches might genuinely hold the line.
read miss, no sharers -> E read miss, sharers exist -> S E, local write -> M (no bus transaction) S, local write -> M (invalidate broadcast required)
The common pattern of “read a private object into a register, then modify it” hits Exclusive-to-Modified constantly: thread-local counters, stack variables that leak into cache, and any data structure that is genuinely private to one thread all benefit. MESI is the protocol actually implemented (in some variant) by most modern x86 and ARM CPUs, precisely because this uncontended read-then-write pattern dominates in real code far more often than genuine cache-line sharing does.