Interrupt masking defers selected hardware events through bits in %status. ivss uses bit zero for the timer, bit one for the terminal, and bit two as the shared hardware mask:
csrrd %status, %r1 ld $5, %r2 # bits 0 and 2 or %r2, %r1 csrwr %r1, %status
This sets the timer and global bits while retaining other status bits. A set mask disables delivery; it does not enable that source. Clearing the relevant bits permits delivery again when a request is pending and a handler exists.
The hardware cases explicitly check the shared and source-specific masks:
if ((CSR[STATUS] & ST_MASK_INTERRUPTS) || (CSR[STATUS] & ST_MASK_TIMER)) continue;
A masked request remains pending because delivery, rather than masking, clears its flag. Timer and terminal entry set the global mask in the handler's status; the return frame retains the previous status for iret.
Software and invalid-instruction cases do not use these hardware-mask checks. The emulator's internal INT_ENA state is a separate gate, not another named control register.
Source: emulator.c.