Memory bandwidth is the rate at which data moves through memory. An FDTD update reads field samples and coefficients and writes updated values. For large grids, moving these arrays can limit throughput even when arithmetic capacity remains available.
FDTD CUDA supplies a traffic model for each backend. If $B$ is the modeled number of bytes transferred per step, $N$ is the step count, and $t$ is elapsed time, the effective bandwidth is:
$$ \mathrm{BW}_{\mathrm{effective}}=\frac{NB}{t} $$
Dividing by $10^9$ expresses the result in GB/s. This estimate comes from the update's modeled traffic, rather than hardware counters measuring actual DRAM transfers. Cache reuse and access patterns affect how the model relates to physical memory traffic.
Coefficient reuse reduces repeated coefficient loads, while tiling reuses magnetic values within a CUDA block. Both can improve throughput by reducing traffic per update. The backend also reports GPU peak bandwidth and a device-copy measurement to provide comparison points.