# L1 cache

**[L1 cache](https://en.cppreference.com/w/cpp/memory/cpu_cache)** is the first and fastest level of the cache hierarchy, sitting directly next to a single core with latency of 4-5 cycles. It is intentionally small (typically 32–64 KB) to maintain low latency and is almost always split into separate instruction (L1i) and data (L1d) caches to allow simultaneous instruction fetch and data access.

L1 is private to each core, which keeps access latency low but means the same cache line can be duplicated across cores' L1s, requiring cache-coherence protocols to manage consistency.

## Example

This example demonstrates L1 cache effects on access latency through strided memory access patterns.

```c
// compile: gcc -O2 -o l1cache l1cache.c
// run: ./l1cache
// description: measure L1 cache hits vs misses with different stride patterns

#include <stdio.h>
#include <time.h>

#define ARRAY_SIZE 16384  // 16KB, fits in L1

int main() {
    int arr[ARRAY_SIZE];
    clock_t start, end;
    volatile int sum = 0;
    
    // Sequential access (good locality, L1 hits)
    start = clock();
    for (int i = 0; i < ARRAY_SIZE; i++) {
        sum += arr[i];
    }
    end = clock();
    printf("Sequential: %ld cycles\n", end - start);
    
    // Strided access (poor locality, L1 misses)
    start = clock();
    for (int i = 0; i < ARRAY_SIZE; i += 8) {
        sum += arr[i];
    }
    end = clock();
    printf("Strided: %ld cycles\n", end - start);
    
    return 0;
}
```