# Hardware Integration and QPUs

**Hardware integration** allows targeting real quantum processors (IonQ, IQM, etc.) via CUDA-Q's backend abstraction. Same kernel code runs on simulators or hardware with minimal changes.

```cpp
#include "cudaq.h"
#include <string>

// Hardware-agnostic kernel
struct HardwareKernel {
  void operator()() __qpu__ {
    cudaq::qvector q(5);
    
    // Standard gates (available on most QPUs)
    for (int i = 0; i < 5; i++) {
      h(q[i]);
    }
    
    // CNOT chain (common connectivity)
    for (int i = 0; i < 4; i++) {
      cx(q[i], q[i+1]);
    }
    
    mz(q);
  }
};

int main() {
  // Step 1: Test on simulator
  printf("Testing on GPU simulator...\n");
  cudaq::set_target("nvidia");
  auto sim_result = cudaq::sample<HardwareKernel>(1000);
  printf("Simulator result: success\n");
  
  // Step 2: Test on noisy simulator (realistic hardware)
  printf("Testing on noisy simulator...\n");
  cudaq::noise_model noise;
  noise.add_channel<cudaq::channels::depolarizing>({"h", "cx"}, 0.001);
  cudaq::set_target("density_matrix");  // Mixed state backend
  auto noisy_result = cudaq::sample<HardwareKernel>(1000);
  printf("Noisy result: success\n");
  
  // Step 3: Deploy to real hardware
  printf("Deploying to hardware...\n");
  // Set credentials for quantum service
  cudaq::set_target("iqm");  // IQM backend (or "ionq", "ibm", etc.)
  
  // Submit job to hardware (async)
  // auto job = cudaq::sample_async<HardwareKernel>(1000);
  
  // Wait for results (may take minutes)
  // auto hw_result = job.get();
  // printf("Hardware result received\n");
  
  // For now, just show the connection would succeed
  printf("Hardware target configured: iqm\n");
  
  return 0;
}
```

## Hardware Considerations

1. **Gate set**: Different QPUs support different native gates
2. **Connectivity**: Not all qubits connect; may require SWAP gates
3. **Coherence**: Limited by T1, T2 times (typically microseconds)
4. **Queue times**: Real hardware has queues; simulation is immediate

CUDA-Q abstracts these differences, but understanding hardware constraints improves algorithm design.